1. Field of the Invention:
The present invention relates to the field of content addressable memories, associative storage, parallel-search storage, and memory cells.
2. Description of Related Art.:
Content addressable memories (CAMs) are used in computer data processing to identify the location of the data stored in the memory by specifying part or all of its contents. When a match is found in a CAM array chip, the chip sends an output to its match line indicating that a match is found in that CAM array chip.
FIG. 1A presents a prior art CAM cell 100. CAM cell 100 includes two data latch units I1 and I2, each of which is an inverter which may be implemented by the circuit shown in FIG. 1B. CAM cell 100 includes a data word match line (match) 101, a read/write row select line (rsel) 102, a read/write column select line (csel) 104, a data bit line (bit) 103 used for a read, write or match operation, and a data bit bar line (bitb) 105 used for a read, write or match operation. Bitb 105 may or may not be complementary to bit 103.
Rsel 102 and csel 104 must both be a logic 1 to read or write to CAM cell 100. A WRITE operation is accomplished using the series transistors N5 and N6 connected to bit 103, and transistors N7 and N8 connected to bitb 105. Writing data to CAM cell 100 requires overcoming the crowbar current in I1 and I2. It is crucial to have proper width-to-length ratios of transistors in I1 and I2 and transistors N5, N6, N7 and N8, to ensure adequate drive in WRITE transistors (N5, N6, N7 and N8) and to prevent a read disturbance problem caused by too much drive.
During a MATCH operation, bit 103 and bitb 105 are precharged to a logic 0 (e.g. V.sub.ss), and match 101 is precharged to a logic 1 (e.g. V.sub.cc). After a data pattern is presented on bit 103 and bitb 105, match 101 for a row is pulled low if the data in any of the cells on the row does not match the pattern on bit 103 and bitb 105. It will be appreciated that in alternative CAM cells (not shown), the logic conventions may be different such that logic 0 corresponds to V.sub.cc and logic 1 corresponds to V.sub.ss or that the bit line may be precharged to logic 1 during a MATCH operation.
The disadvantages of CAM cell 100 include the following: First, a large crowbar current can occur during a WRITE operation when a large number of cells are written simultaneously. This results in large surges in the power supply current for the IC chip which contains the CAM. Second, csel 104 must be activated for both read and write operations. Third, internal nodes 106 and 107 share charges with bit 103 and bitb 105, respectively. This charge-sharing can create a large read access time pushout. Fourth, the precharge states on bit 103 and bitb 105 are not consistent for all operations. Finally, sizing of width-to-length length ratios of transistors in I1 and I2 and transistors N5, N6, N7 and N8 is sensitive to having a proper write operation and eliminating a read disturbance problem.
FIG. 2 presents another prior art CAM cell 119 described in Anthony J. McAuley and Charles J. Cotton, "A Self-Testing Reconfigurable CAM," IEEE Journal of Solid-State Circuits 26(3) pp. 257-261 (March 1991). In CAM cell 119, transistors P12 and P14 are used to turn off the current path from Vcc to ground in I21 and I22 during a WRITE operation to limit the crowbar current. CAM cell 119 includes a write parallel line (wp) 120, a read/write word select line (ws) 121, a data word match line (match) 122, a data bit line (bit) 123 used for a read, write or match operation, and a data bit bar line (bitb) 124 used for a read, write or match operation. Bitb 124 may or may not be complementary to bit 123.
One disadvantage of CAM cell 119 is that it does not have the read/write column select capability. In addition, the precharge states on bit 123 and bitb 124 are not consistent for all operations.
Another prior art CAM cell (not shown) incorporates dynamic CMOS instead of fully static CMOS devices. However, dynamic CAM cells are disadvantageous because they have the same disadvantages as other dynamic memory cells compared to static CMOS memory cells, including but not limited to refresh requirements, read disturb and noise susceptibility.
To overcome the drawbacks of the prior art, the present invention provides fully static CAM cells operating at low power during a WRITE operation. In the present invention, data can be simultaneously written to a very large number of CAM cells without causing a power surge. The present invention also has features that help to manage the power consumed during other CAM operations by having consistent precharge states for bit and bitb lines for all CAM cell operations. In addition, the present invention includes selective column write capability for writing data to a selected column.